Chinese Researchers Develop Miniscule Graphene-MoS2 Transistors

Researchers Develop Miniscule Graphene-MoS2 Transistors
Image credit: Nature

Researchers from China’s Tsinghua University and East China Normal University have created a transistor with the smallest gate length ever reported. This milestone was made possible by using graphene and molybdenum disulfide and stacking them into a staircase-like structure with two steps.

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Transistors have a few core components: the source, the drain, the channel, and the gate. Electrical current flows from the source, through the channel, past the gate, and into the drain. The gate switches this current on or off depending on the voltage applied to it.

On the higher step, there is the source, and on top of the lower step, there is the drain. Both are made of a titanium palladium alloy separated by the surface of the stairs, which is made of a single sheet of a molybdenum disulfide (MoS2), itself resting on a layer of hafnium dioxide that acts as an electrical insulator, reports GrapheneInfo.

The interior of the higher step is a sandwich of aluminum covered in aluminum oxide, which rests on top of a graphene sheet. The aluminum oxide acts as an electrical insulator, except for a small gap in the vertical wall of the higher step, where the graphene sheet is allowed to contact the molybdenum disulfide. The entire staircase structure rests on a thick layer of silicon dioxide.

A university building
Tsinghua University, China

The trick to this design is that the edge of the graphene sheet is used, which means that when the gate is set to the “on” state, it’s only 0.34 nm wide—essentially the width of the graphene layer itself. Another notable feature of this “side-wall transistor” is its negligible current leakage due to higher off-state resistance. Manufacturers could leverage this quality for low-power applications. Best of all, it would be relatively easy to make, although many of the prototypes required quite a bit of voltage to drive.

The research team believes going smaller than 0.34 nm for the gate size is almost impossible.

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The researchers behind the new transistor managed to prove that a functional transistor could be made using one-atom thin materials without inventing a new process for precision positioning of the required layers. However, reliably building billions of these side-wall transistors is still a major challenge.

In the meantime, many companies are working on making gate-all-around (GAA-FET) transistors a reality and standardizing interconnects for chiplet designs.

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Cathy Russey
Cathy Russey () is Online Editor at WT | Wearable Technologies and specialized in writing about the latest medical wearables and enabling technologies on the market. Cathy can be contacted at info(at)